Government gives permission to 7 startups for chip designing, Digital India RISC-V program launched

The campaign for chip manufacturing in India has started picking up pace. The government has given permission for chip designing to seven startups of the country. Minister of State for Electronics and IT, Rajeev Chandrasekhar gave this information on Saturday. The minister said that on the second day of ‘Semicon India 2023’  India has a bright future in the global semiconductor ecosystem. According to the news of IANS, the government’s target is to establish a strong and internationally competitive presence in the international ecosystem in the next 10 years. Under this, seven chip design startups have been approved for finance and assistance in developing their products.

RISC-V program launched

< p>According to the news, the Union Minister said that the government has launched a Digital India RISC-V program and a large number of startups and incubation centers around educational institutions are looking forward to the future of RISC-V and  ;Focusing on powered device. This government initiative is a new opportunity for startups to delve deeper into deep technology and semiconductor design.

Intent on developing new life-changing technologies

< p>Arm India President Guru Ganesan said that innovative silicon startups will drive the future of the semiconductor industry as they develop life-changing new technologies in areas ranging from AI to autonomous vehicles and IoT. Two more startups/MSMEs involved in semiconductor design (chip designing) have been announced as participants of the ‘SemiconIndia FutureDesign DLI’ scheme. One of these is Ahisa Digital Innovations Pvt Ltd (Ahisa), based in Chennai, which focuses on telecommunication, networking and cyber security domains. Another startup is Bengaluru-based Caligo Technologies that serves international companies in the HPC, Big Data and AI/ML segments.

Design Infrastructure

DLI The scheme (DLI Scheme) targets Integrated Circuits (ICs), Chipsets, System on Chips (SoC), Systems and Semiconductor Design for IP Core and Semiconductor Linked Design with financial support at different stages of development and deployment  Along with the design is to provide infrastructure support. Collaboration was also initiated through an MoU between the Center for Nano Science and Engineering (CeNSE) at the Indian Institute of Science (IISc), Bengaluru and LAM Research India.


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